1. Field of the Invention
The present invention relates to a thin film transistor used in a liquid crystal display device or a display device which utilizes organic electro-luminescence, and to a method of manufacturing the thin film transistor.
2. Description of the Background Art
A thin film transistor (TFT) used in a liquid crystal display device or a display device which utilizes organic electro-luminescence has a structure in which a gate insulating film is formed on an island-like semiconductor layer and a gate electrode is formed on the gate insulating film.
More specifically, the gate insulating film is formed to be shaped like eaves in section thereof because of poor step coverage of the gate insulating film over a stepped portion of the semiconductor layer.
Then, to form the gate electrode on the gate insulating film by carrying out dry etching on the gate electrode would cause a portion of the gate electrode which is present under eaves formed of the gate insulating film to remain un-etched as a residue. Such residue is likely to be short-circuited to an adjacent wire.
On the other hand, to form the gate electrode on the gate insulating film by carrying out wet etching on the gate electrode would cause an etchant to run through a back side of the gate electrode around the stepped portion of the semiconductor layer. As a result, etching on the gate electrode proceeds from both a front side and a back side thereof, to cause a problem of disconnection of the gate electrode.
To solve the above-noted problems, according to the invention described in Japanese Patent Application Laid-Open No. 2004-64060 (which will hereinafter be referred to as “JP No. 2004-64060), a semiconductor layer is tapered with a width thereof decreasing as a distance from a bottom increases. In JP No. 2004-64060, by tapering the semiconductor layer, step coverage of a gate insulating film is improved, to thereby suppress a residue of a gate electrode formed on the gate insulating film, and alleviate the problem of disconnection of the gate electrode.
According to the invention described in Japanese Patent Application Laid-Open No. 2000-77665 (which will hereinafter be referred to as “JP No. 2000-77665”), a semiconductor layer is tapered and Ar or the like is implanted into a tapered portion of the semiconductor layer.
According to the invention described in Japanese Patent Application Laid-Open No. 2000-332254 (which will hereinafter be referred to as “JP No. 2000-332254”), a semiconductor layer is tapered, and Ar or the like is implanted into a tapered portion of the semiconductor layer. Further, an oxide film is subsequently formed.
According to the invention described in Japanese Patent Application Laid-Open No. 2003-258262 (which will hereinafter be referred to as “JP No. 2003-258262”), a semiconductor layer is tapered, and impurities of the same conductivity type as a channel are implanted into a tapered portion of the semiconductor layer at a dose which is two to five times a dose of impurities contained in the channel.
In a thin film transistor described in JP No. 2004-64060, however, a channel is formed in a thin portion of the tapered semiconductor layer at a low gate voltage, to turn on the corresponding portion. Namely, the thin portion of the semiconductor layer is turned on in advance of a portion of the semiconductor layer in which a principal part of the channel is formed.
Accordingly, a hump is likely to occur in a line indicating so-called subthreshold characteristics (Ig-Vg characteristics). As a result, it becomes difficult to control a threshold voltage (Vth), to make electrical characteristics of the transistor unstable.
Further, a leakage current is likely to flow between a source and a drain in the tapered portion of the semiconductor layer, to degrade the electrical characteristics of the TFT.
On the other hand, in the invention described in JP No. 2000-332254, the tapered portion of the semiconductor layer is oxidized. Accordingly, the semiconductor layer expands so that the volume thereof increases to approximately twice the original volume thereof. Hence, an additional stepped portion is formed in a side wall of the semiconductor layer, to cause troubles in forming a gate electrode.
Also, in the invention described in JP No. 2000-77665 or JP No. 2003-258262, etching is carried out on a resist while tapering the resist in order to taper the semiconductor layer. As such, it is difficult to control a width of an upper portion (i.e., channel width) of the semiconductor layer.